1. Field of the Invention
The present invention concerns a novel circuit for the demodulation of m-Phase Shift Keying (m-PSK) modulated signals.
2. Description of the Related Art
Phase-Shift Keying (PSK) modulation is widely used to transmit binary data by means of such communication links as terrestrial and satellite microwave links, and computer-to-computer links. The demodulation circuit necessitated by this type of modulation contributes significantly to the overall complexity of receiving equipment. Furthermore, it is widely recognised that a digital implementation is preferable to an analog implementation on the basis of performance insensitivity to environment, performance reproducibility, production costs, integration level and reliability. Consequently, a fully digital demodulation circuit is desirable for demodulating PSK-modulated signals.
Certainly, digital demodulating circuits have already been constructed in the past. However, the techniques employed until now exhibit one major constraint: the sampling rate and the clock frequency of the synchronous digital circuitry must be at least an order of magnitude (usually sixteen to thirty-two times) greater than the rate of the symbols to be demodulated. Conversely, the maximum symbol rate achievable by a digital demodulation circuitry is at least an order of magnitude lower than the maximum clock signal rate achievable by a given technology (CMOS, ECL, etc . . . ).
In practice, this type of fully digital demodulator is used for low data rate signals. High data rate signals required partly or fully analog demodulation circuitry.
Known demodulators for phase shift keying modulated signals comprise substantially a sampling and quantization circuit for sampling and quantizing the analog signal and a carrier recovery circuit for reconstructing the carrier to be served for demodulating the received signal. Known demodulators can be classified into two classes.
The first class includes those demodulators which process input signals whose center frequency is greater than the modulation symbol rate. One-bit quantization of the intermediate frequency signal is compatible with low demodulation losses provided that the sampling frequency is at least an order of magnitude larger than the carrier frequency. This type of demodulator does not need automatic gain control and implements a fully digital carrier tracking loop, which loop reconstructs the carrier by adding or skipping cycles of the master clock. The ratio of master clock frequency to modulation symbol rate determines the phase resolution of the carrier tracking loop and consequently affects the demodulation losses. A ratio of thirty-two results in a carrier phase error as large as 11 degrees. Although the circuit is simple in terms of implementation, its main limitation resides in the requirement for a master clock being several times faster than the modulation symbol rate.
The second class of digital demodulators includes those demodulators which process the in-phase I and the in-quadrature Q components of the baseband input signals. The main limitation of this type of demodulator is that it must include external analog components such as voltage controlled oscillators and gain controlled amplifiers. Furthermore, these external circuits need analog control signals and thus require digital-to-analog conversion circuitries.